1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor manufacturing and, more particularly, to test structures formed in a semiconductor device useful in evaluating possible device design parameters.
2. Description of the Related Art
In a semiconductor device, an interconnect structure consisting of a network of conductive lines connected by vias transmitting signals among various layers of the device. As circuit dimensions shrink to provide devices with more and more functionality, the conductive lines used in interconnect structures decrease in width accordingly. As these conductive lines shrink in width, the conductive lines become more susceptible to effects, such as electromigration, which may result in voids formatting in the conductive lines. Physical stresses can also form the voids, such as thermal stresses resulting from differences in temperature coefficients between dielectric layers and metallization layers.
A void generally refers to a decrease in the volume of metal in the conductive path of the line that results in increased line resistance which may in turn lead to signal degradation and, ultimately, device failure. Therefore, test structures designed to detect voids are commonly incorporated into device designs at the wafer level. A conventional test structure may include a conductive line in one metal layer coupled by a single conductive via to a conductive line having a different line width in another metal layer. The parameters of the test structure, such as the widths of the conductive lines, as well as the dimensions of the via, are chosen to mirror those that will likely be used in a final design.
Such test structures typically allow voids to be detected by providing test points (probe pads) allowing line and/or via resistance to be monitored during a test process. The test process may involve taking baseline line/via resistance measurements (using the probe pads) prior to placing a wafer containing the test structure in an oven to generate, in an accelerated manner, the type of thermal stress a device may encounter during its operational lifetime. After stressing the wafer in the oven (e.g., for several days at a given temperature or cycle of temperatures), resistance measurements may be repeated and compared to the baseline measurements. Any increasing “shift” in the resistance measurements may indicate the presence of voids formed in the lines and/or vias caused by the temperature stressing.
Such a test process may be used both during the manufacturing stage to detect voids and identify failing devices, as well as during the design stage to help determine design parameters (e.g., line widths, via sizes, via/line densities, and via/line ratios) that result in a reliable device. In other words, due to the complex nature of the physical stresses on a conductive line, characterizing or predicting the stresses caused by any particular combination of design parameters is extremely difficult. Therefore, stress testing different parameter combinations in a device to determine their reliability would be desirable.
The simple design of the conventional test structures limits their utility to test different combinations of parameters. In order to evaluate multiple combinations of different line widths and via sizes, multiple test structures would have to be constructed, each utilizing a different combination of potential design parameters to be evaluated. However, constructing multiple test structures is time consuming and expensive.
Accordingly, what is needed is a single test structure that facilitates the evaluation of multiple design parameters.